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data sheet ics843051ag revision a october 13, 2010 1 ?2010 integrated device technology, inc. femtoclock ? crystal-to-3.3v lvpecl clock generator ics843051 general description the ics843051 is a gigabit ethernet clock generator. the ics843051can synthesize 10 gigabit ethernet, sonet, or serial ata reference clock frequencies with the appropriate choice of crystal and output divider. the ics843051 has excellent phase jitter performance and is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. features ? one differential 3.3v lvpecl output ? crystal oscillator interface designed for 18pf parallel resonant crystals ? rms phase jitter at: 155.52mhz (12khz ? 20mhz): 0.74ps (typical) 156.25mhz (1.875mhz ? 20mhz): 0.43ps (typical) 161.13mhz (1.933hz ? 20mhz): 0.43ps (typical) offset noise power ? 100hz -95 dbc/hz 1khz -110 dbc/hz 10khz -125 dbc/hz 100khz -125 dbc/hz ? full 3.3v output supply mode ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages frequency table inputs output frequency range (mhz) crystal frequency (mhz) freq_sel 20.141601 0 161.132812 20.141601 1 80.566406 19.53125 0 156.25 19.53125 1 78.125 19.44 0 155.52 19.44 1 77.76 18.75 0 150 18.75 1 75 1 2 3 4 8 7 6 5 v cca v ee xtal_out xtal_in v cc q0 nq0 freq_sel pin assignment ics843051 8 lead tssop 4.40mm x 3.0mm x 0.925 package body g package top view phase detector vco 0 4 (default) 1 8 32 (fixed) q0 nq0 xtal_in xtal_out osc block diagram
ics843051ag revision a october 13, 2010 2 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator table 1. pin descriptions note: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = 0c to 70c number name type description 1v cca power analog supply pin 2v ee power negative supply pin. 3, 4 xtal_out xtal_in input crystal oscillator interface. xtal_i n is the input, xtal_out is the output. 5 freq_sel input pulldown frequency select pin. lvcmos/lvttl interface levels. 6, 7 nq0, q0 output differ ential output pair. l vpecl interface levels. 8v cc power core supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k ? item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuos current surge current 50ma 100ma package thermal impedance, ja 101.7 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v i cc power supply current 70 ma i cca analog supply current 15 ma i ee power supply current 85 ma
ics843051ag revision a october 13, 2010 3 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator table 3b. lvcmos/lvttl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = 0c to 70c table 3c. lvpecl dc characteristics, v cc = 3.3v 5 %, v ee = 0v, t a = 0c to 70c note 1: outputs termination with 50 ? to v cc ? 2v. table 4. crystal characteristics ac electrical characteristics table 5. ac characteristics, v cc = 3.3v 5%, v ee = 0v, t a = 0c to 70 note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: please refer to phase noise plot. symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current v cc = v in = 3.465v 150 a i il input low current v cc = 3.465v, v in = 0v -5 a symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 12 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf symbol parameter minimum typical maximum units f out output frequency 155.52 mhz 156.25 mhz 161.13 mhz t jit(?) rms phase jitter, random; note 1 155.52mhz, integration range: 12khz ? 20mhz 0.74 ps 156.25mhz, integration ran ge: 1.875mhz ? 20mhz 0.43 ps 156.25mhz, integration range: 12khz ? 20mhz 0.75 ps 161.13mhz, integration ran ge: 1.933mhz ? 20mhz 0.43 ps 161.13mhz, integration range: 12khz ? 20mhz 0.72 ps t r / t f output rise/fall time 20% to 80% 325 600 ps odc output duty cycle 49 51 %
ics843051ag revision a october 13, 2010 4 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator typical phase noise at 155.52mhz noise power dbc hz filter phase noise result by adding a filter to raw data raw phase noise data ? ? ? 155.52mhz rms phase jitter (random) 12khz to 20mhz = 0.74ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843051ag revision a october 13, 2010 5 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator typical phase noise at 156.25mhz gb ethernet filter phase noise result by adding a gb ethernet filter to raw data raw phase noise data ? ? ? 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.43ps (typical) noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843051ag revision a october 13, 2010 6 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator typical phase noise at 161.13mhz filter phase noise result by adding a filter to raw data raw phase noise data ? ? ? 161.13mhz rms phase jitter (random) 1.933mhz to 20mhz = 0.43ps (typical) noise power dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m offset frequency (hz)
ics843051ag revision a october 13, 2010 7 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator parameter measureme nt information 3.3v lvpecl output load ac test circuit output duty cycle/pulse width/period rms phase jitter output rise/fall time scope qx nqx lvpecl v ee v cc v cca 2v -1.3v0.165v nq0 q0 t pw t period t pw t period odc = x 100% phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 20% 80% 80% 20% t r t f v swing nq0 q0
ics843051ag revision a october 13, 2010 8 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator applications information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ics843051 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc and v cca should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v cca pin. figure 1. power supply filtering crystal input interface the ics843051 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 26.04167mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 2. crystal input interface v cc v cca 3.3v 10 ? 10f .01f .01f xtal_in xtal_out x1 18pf parallel crystal c1 33pf c2 27pf
ics843051ag revision a october 13, 2010 9 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedance of t he driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpec l driver to xtal input interface r2 100 r1 100 rs 43 ro ~ 7 ohm driv er_lvcmos zo = 50 ohm c1 0.1uf 3.3v 3.3v cry stal input interf ace xta l _ i n xta l _ o u t cry stal input interf ace xtal_in xtal_out r3 50 c1 0.1uf r2 50 r1 50 zo = 50 ohm lvpecl zo = 50 ohm vcc=3.3v
ics843051ag revision a october 13, 2010 10 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics843051ag revision a october 13, 2010 11 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator schematic example figure 5a shows a schematic example of the ics843051. an example of lvepcl termination is shown in this schematic. additional lvpecl te rmination approaches are shown in the lvpecl termination application note. in this example, an 18pf parallel resonant crystal is used. the c1 = 27pf and c2 = 33pf are recommended for frequency accuracy. the c1 and c2 values may be slightly adjusted for optimizing frequency accuracy. figure 5a. ics843051 schematic example pc board layout example figure 5b shows an example of ics843051 p.c. board layout. the crystal x1 footprint shown in this example allows installation of either surface mount hc49s or through-hole hc49 package. the footprints of other components in this example are listed in the table 6. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. figure 5b. ics843051 pc board layout example table 6. footprint table note: table 6 lists component sizes shown in this layout example. r4 82.5 r1 1k c4 0.01u vcc + - vcc zo = 50 ohm r6 82.5 c1 27pf c3 10uf 1 8 p f zo = 50 ohm c2 33pf r2 10 vcc r3 133 u1 ics843051i 1 2 3 4 8 7 6 5 vcca vee xta l _ o u t xta l _ i n vcc q0 nq0 freq_sel c5 0.1u q vcca r5 133 vcc nq x1 19.44mhz reference size c1, c2 0402 c3 0805 c4, c5 0603 r2 0603
ics843051ag revision a october 13, 2010 12 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator power considerations this section provides information on power dissipa tion and junction temperature for the ics843051. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843051 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 85ma = 294.5mw power (outputs) max = 30mw/loaded output pair total power_ max (3.465v, with all outputs s witching) = 294.5mw + 30mw = 324.5mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.324w * 90.5c/w = 99.3c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resitance ja for 8 lead tssop, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
ics843051ag revision a october 13, 2010 13 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50
ics843051ag revision a october 13, 2010 14 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator reliability information table 8. ja vs. air flow table for a 8 lead tssop transistor count the transistor count for ics843051 is: 1892 package outline and package dimensions package outline - g suffix for 8 lead tssop table 9. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics843051ag revision a october 13, 2010 15 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843051ag 3051a 8 lead tssop tube 0 c to 70 c 843051agt 3051a 8 lead tssop 2500 tape & reel 0 c to 70 c 843051aglf 051al ?lead-free? 8 lead tssop tube 0 c to 70 c 843051AGLFT 051al ?lead-free? 8 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics843051ag revision a october 13, 2010 16 ?2010 integrated device technology, inc. ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator revision history sheet rev table page description of change date a t10 14 ordering information table - corrected count from 154 per tube to 100 per tube. 11/16/04 a t10 1 14 added lead-free bullet in features section. ordering information table - added "lead-free" part. 12/14/04 a t10 14 ordering information table/shipping pa ckaging column - delet ed tube quantity. 1/19/07 a 9 added lvcmos to xtal interface section. 3/5/08 a t3c t5 3 3 9 lvpecl dc characteristics table - corrected v oh /v ol parameters from ?current? to ?voltage? and units from "ua" to "v". ac characteristics table - added thermal note. updated ?overdriving the crystal interface? section. updated header/footer. 10/13/10
ics843051 data sheet femtoclock ? crystal-to-3.3v lvpecl clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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